Digital terminal equipment (DTE), such as computers and facsimile machines, routinely send and receive information and control signals through communications networks (i.e. the telephone network). In order to effectively use the network facilities, however, the DTE must have a means of translating digital data into a form suitable for transmission over the network. Similarly, DTE devices at the receiving end must have a means for translating that signal back into digital form, check for errors, and make use of the information.
The most common data communication equipment (DCE) that provides a DTE with these facilities is a modem. Basically, a modem is capable of modulating and demodulating digital data over a communication medium of a communications network. For example, in communicating over a telephone network, one modem translates the digital data generated by the originating DTE into an analog signal and sends the signal over the telephone network to a second modem at the receiving end. The receiving modem then translates the analog signal back into the digital data at the receiving DTE.
A typical modem architecture is shown in FIG. 1. The typical modem has a controller and a digital signal processor (DSP) which are electrically connected to each other through an interface circuit (i.e. VALV). The DSP and the interface circuit together form a data pump which is responsible for taking the digital data from the controller, modulating or formatting the data, and transmitting the data over the line. The controller provides supervisory functions such as inserting control commands in the data stream, providing data compression, and performing error bit calculations.
As shown in FIG. 1, a typical modem also has a MIMIC and a line status register (LSR) which are electrically connected to the controller data bus. A MIMIC is a circuit that mimics the register set of a universal asynchronous receiver transmitter (UART). The MIMIC contains two large FIFO registers, a receiver channel (Rx) FIFO and transmit channel (Tx) FIFO, that act as data buffers to allow the DTE to communicate asynchronously with the DCE or modem controller. The LSR is basically a register through which transmission error data flows during modem operation.
In a typical modem, data received by the modem passes through the Rx FIFO, whereas data transmitted from the modem passes through the Tx FIFO. The LSR is typically an 8 bit register, wherein three of the eight bits indicate specific errors detected during transmission of a specific 8 bit byte of transmission data. The Rx FIFO of the MIMIC receiver channel is typically 11 bits wide, 8 bits for the transmission data and 3 bits for the error bits from the LSR.
For each 8 bit byte of data received from the transmission line, the controller of a typical present day modem performs a series of interleaved writes to the Rx FIFO and the LSR. That is, as data is received by the modem, the controller first writes the 3 error bits associated with a particular 8 bit byte of data to the LSR, and then writes the 8 bit byte of data to the Rx FIFO. During this FIFO write, however, the three bits located in the LSR are automatically pulled from the LSR, in parallel with the 8 data bits, to fill the 11 bit wide Rx FIFO register. This 11 bit word is then sent to the receiving DTE for processing. The procedure of writing to the LSR and then the FIFO is called an interleaved write. In present day modems, the interleaved write is repeated for each 8 bit byte of data received by the modem.
The automatic interleaved write for all data transfers, however, can cause error bits to be included with the wrong data and it can reduce the available modem timing overhead. For example, when using the MIMIC to transfer memory information from the controller memory to the receiving DTE (i.e. a DMA transfer), there is not a great concern for data error. The memory is highly reliable and usually travels a very short distance without repeaters from controller memory to the local DTE. As a result, it is unnecessary, and thus wasteful for a controller to perform interleaved writes during DMA transfers for each 8 bit byte of data transferred from the controller memory to the MIMIC FIFO. For such DMA data transfers, the modem need only perform a non-interleaved write for the substantial likelihood of a successful transfer of error-free data. That is, the controller need only write the 8 bits of memory data to the FIFO (no LSR write is necessary). This is called a non-interleaved write.
During a non-interleaved write in present day modems, however, the controller uses the same FIFO write instruction to put the memory information into the FIFO as it uses during an interleaved write. As a result, if a present day modem were to attempt a non-interleaved write of a given data word from the modem controller to the FIFO, the error bits that were written into the LSR during the most recent interleaved write would automatically be pulled into the FIFO, and thus become associated with the bits of the given data word. That is, the error bits from an unrelated 8-bit byte of data would become associated with the 8-bits of data sent during the non-interleaved write. As a result, if a present day modem were to attempt to perform a non-interleaved write without some software and/or hardware changes, errors would become associated with data words for which there was no error. Thus, present day modem controllers can not freely perform both non-interleaved and interleaved writes to the same MIMIC Rx FIFO.